Reception circuit

ABSTRACT

A reception circuit includes: an equalizer; a comparator to compare an output signal of the equalizer with first, second, and third thresholds at a first-timing to output first, second, and third comparison-results, respectively; a selector to select any one of the first and second comparison-results based on a determination-result at a timing before the first-timing, and update the determination-result; a detector to detect a phase information based on the first or second comparison-result not selected; a shifter to adjust a sampling clock phase based on the phase information detected; and a controller to set a third threshold based on the first and second thresholds by either adjusting the first and second thresholds based on the output signal amplitude or adding/subtracting a first value to/from the output signal, detect an equalization-result based on the third comparison-result by the set third threshold, and adjust an equalization coefficient based on the detected equalization-result.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2013-222353 filed on Oct. 25,2013, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a reception circuit.

BACKGROUND

With a performance improvement of an information processing apparatus, ahigh-speed data rate of a data signal transmitted and received insideand outside of an apparatus has been achieved in recent years. A datasignal reception circuit determines an amplitude level of a data signalat timing synchronized with a sampling clock and performs datareproduction based on the determination result. When a high speed datarate is implemented, a slight phase deviation occurring between the datasignal and the sampling clock has an influence on an accuracy of datadetection. Accordingly, a technology called a tracking CDR (Clock andData Recovery) which detects the phase deviation and synchronizes aphase of the sampling clock with a phase of the data signal is utilized.The tracking CDR technology includes a technology called a 2× trackingCDR which performs sampling on a 1-bit data twice and a technologycalled a baud rate tracking CDR which performs sampling on a 1-bit dataonce.

The baud rate tracking CDR compares the data signal at an adjacentsampling timing with a total of three threshold values, which includes athreshold value for data determination and two threshold values forphase detection, to detect the phase deviation of the sampling clockwith respect to the data signal. Therefore, three comparators thatcompare the data signal with the threshold values are utilized.

Further, an equalization circuit which compensates the received datasignal so as to suppress deterioration of a reception sensitivity isused in a reception circuit. As one of equalization circuits, there is adecision feedback equalizer (DFE) which determines whether the outputdata is 0 (zero) or 1 (one) and feedbacks and uses the determinationresult so as to suppress amplification of a noise input. Further, thereis a speculative DFE adopted as a scheme of achieving a high operationalspeed of the DFE. The speculative DFE performs an equalization processin advance for all data patterns in a case where the data to be fed backis 0 (zero) or 1 (one). Also, when the data has been fed back, anequalization result corresponding to the data is selected and output.Accordingly, feedback loop processings are reduced and thus the highoperational speed of the DFE is implemented. The speculative DFEutilizes a comparator to determine whether data is 0 or 1. When thenumber of taps is “N”, the number of comparators becomes 2^(N).

When the baud rate tracking CDR and the speculative DFE described aboveare utilized in the reception circuit, the number of comparatorsincreases and thus a circuit scale becomes large.

Related techniques are disclosed in, for example, InternationalPublication Pamphlet No. WO 2008/032492, International PublicationPamphlet No. WO 2010/150624, and Japanese Laid-Open Patent PublicationNo. 2008-301337.

SUMMARY

According to an aspect of the invention, a reception circuit toreproduce a data signal based on a data determination result ofdetermining an amplitude level of an input data signal at a samplingtiming synchronized with a sampling clock, includes: an equalizerconfigured to perform an equalization process on the input data signal;a comparator configured to compare an output data signal of theequalizer with a first threshold value, a second threshold value, and athird threshold value at a first sampling timing to output a firstcomparison result, a second comparison result, and a third comparisonresult, respectively; a selector configured to select any one of thefirst comparison result and the second comparison result based on thedata determination result at a second sampling timing before the firstsampling timing, and update the data determination result; a phasedetector configured to detect a phase information based on the firstcomparison result or the second comparison result which is not selectedby the selector; a phase shifter configured to adjust a phase of thesampling clock based on the phase information detected by the phasedetector; and a controller configured to set a third threshold valuebased on the first threshold value and the second threshold value byeither adjusting the first threshold value and the second thresholdvalue based on the amplitude of the output data signal or adding orsubtracting a first value to or from the output data signal, detect anequalization result at the equalizer based on the third comparisonresult by the set third threshold value, and adjust an equalizationcoefficient of the equalizer based on the detected equalization result.

The object and advantages of the invention will be realized and attainedby means of the elements and combinations particularly pointed out inthe claims.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and arenot restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a view illustrating an exemplary reception circuit accordingto a first embodiment;

FIG. 2 is a view illustrating an exemplary selector;

FIG. 3 is a view illustrating examples of adjustments of two thresholdvalues for DFE;

FIG. 4 is a view explaining an example of a data determination process,a phase detection process and a phase adjustment process;

FIG. 5 is a view illustrating an example of a phase detection algorithm;

FIG. 6 is a view illustrating an example of threshold value for errordetection;

FIG. 7 is a view illustrating an example of an output data signal of anequalizer when an equalization level is low;

FIG. 8 is a view illustrating an example of an output data signal of anequalizer after optimization of an equalization level;

FIG. 9 is a view illustrating the example of an output signal of aselector after a phase adjustment and an equalization level optimizationin an analog waveform;

FIG. 10 is a view illustrating an exemplary reception circuit accordingto a second embodiment;

FIG. 11 is a view illustrating an example of a threshold value settingfor DFE in the reception circuit according to the second embodiment;

FIG. 12 is a view illustrating another example of the phase detectionalgorithm;

FIG. 13 is a view illustrating an exemplary selector in the receptioncircuit according to the second embodiment;

FIG. 14 is a view illustrating an exemplary reception circuit accordingto a third embodiment; and

FIG. 15 is a view illustrating an exemplary reception circuit accordingto a fourth embodiment.

DESCRIPTION OF EMBODIMENTS

Hereinafter, exemplary embodiments of the present disclosure will bedescribed with reference to accompanying drawings.

First Embodiment

FIG. 1 is a view illustrating an exemplary reception circuit accordingto a first embodiment of the present disclosure. A reception circuit 1is provided with functionalities of a 1-tap speculative DFE and a baudrate tracking CDR, and includes an equalizer 2, a comparator 3, ade-multiplexer (hereinafter, denoted by a “DMX”) 4, a selector 5, aphase detector 6, a filter 7, a phase shifter 8, and a controller 9.

The equalizer 2 performs an equalization process on an input data signalDi. The comparator 3 compares an output data signal of the equalizer 2with three threshold values at a certain sampling timing and outputs thecomparison results. The comparator 3 includes three comparators 3-1, 3-2and 3-3. The comparator 3-1 compares the output data signal of theequalizer 2 with a first threshold value for DFE and outputs acomparison result Dn. The comparator 3-2 compares the output data signalof the equalizer 2 with a second threshold value for DFE and outputs acomparison result Dp. The second threshold value is greater than thefirst threshold value in the reception circuit 1 of the firstembodiment. The comparator 3-3 compares the output data signal of theequalizer 2 with a threshold value for error detection and outputs acomparison result ERR.

The DMX 4 performs inverse multiplexing on 1-bit comparison results ERR,Dp and Dn to be divided into n bits, and supplies theinverse-multiplexed comparison result ERR to the controller 9 andsupplies the inverse-multiplexed comparison results Dp and Dn to theselector 5 and the phase detector 6, respectively. Inverse multiplexingis a technique which divides a single stream of data into multiplestreams of data. The selector 5 selects any one of the comparisonresults Dn and Dp based on a result of the data determination at asampling timing before one of the sampling timing used in the comparator3 and updates the data determination result Do. For example, when thedetermination result Do at the timing before one of the sampling timingis 0, the comparison result Dn is selected at the current samplingtiming and when the determination result Do at the timing before one ofthe sampling timing is 1, the comparison result Dp is selected at thecurrent sampling timing.

The phase detector 6 detects a phase information UP/DN based on thecomparison result Dn or Dp which is not selected in the selector 5. Forexample, the phase detector 6 detects the phase information UP/DNdepending on whether the comparison result Dn or Dp which is notselected in the selector 5 is 1 or 0. A phase detector used as the phasedetector 6 is not a Mueller-Muller (MM) phase detector which detects thephase from the amplitude used in a baud rate tracking CDR, but aBang-Bang (BB) type phase detector which detects the phase informationfrom data edge information.

For example, when a data pattern is a 3-bit continuous data that is“011”, the comparison result Dn is used for the data determination atthe sampling timing for the second bit, and thus the phase informationUP/DN is detected based on the comparison result Dp which is not usedfor the data determination. For example, when the comparison result Dpis 1, it is determined that the phase of the sampling clock CLKs lagsbehind the phase of the output data signal of the equalizer 2. In thiscase, the phase detector 6 sets the phase information UP/DN, forexample, as “+1”. When the comparison result Dp is 0, it is determinedthat the phase of the sampling clock CLKs is ahead of the output datasignal of the equalizer 2. In this case, the phase detector 6 sets thephase information UP/DN, for example, as “−1”.

The filter 7 filters the phase information UP/DN to generate a phaseadjustment code Pcode. In the meantime, the filter 7 is not limited to adigital filter and may be a circuit which includes for example, a chargepump which adjusts electric current according to the phase informationUP/DN, and converts and outputs the adjusted current value into avoltage value.

The phase shifter 8 generates a sampling clock CLKs from an input clockCLKin. Further, the phase shifter 8 receives the phase adjustment codePcode as an input and adjusts the phase of the sampling clock CLKs basedon the phase information UP/DN detected by the phase detector 6. Forexample, when the phase information UP/DN is “+1”, the phase shifter 8advances the phase of the sampling clock CLKs, and when the phaseinformation UP/DN is “−1”, the phase shifter 8 delays the phase of thesampling clock CLKs.

The controller 9 adjusts the first threshold value and the secondthreshold value for DFE based on amplitude of the output data signal ofthe equalizer 2. The controller 9 may detect the amplitude of the outputdata signal of the equalizer 2 from a threshold value at the time whenthe comparison result ERR of the threshold value with the output datasignal is switched from 0 to 1 or from 1 to 0 by changing the thresholdvalue for error detection. Further, the controller 9 adjusts the firstthreshold value and the second threshold value based on the detectedamplitude in the reception circuit 1 of the first embodiment. An exampleof a threshold value adjustment method will be described in later (seeFIG. 3).

Further, the controller 9 sets the threshold value for error detectionbased on the adjusted first threshold value and second threshold valuefor DFE, detects the equalization result in the equalizer 2 based on thecomparison result ERR by the set threshold value for error detection,and adjusts an equalization coefficient Ceq based on the detectedequalization result.

When setting a threshold value for error detection, the controller 9sets the threshold value for error detection to a value obtained byadding or subtracting an expectation value of the amplitude of theoutput data signal from the equalizer 2 to or from, for example, each ofthe first threshold value and the second threshold value. Also, thecontroller 9 adjusts the equalization coefficient Ceq of the equalizer 2so as to cause a probability of occurrence of 0 (zero) to be equal tothat of 1 (one) in the comparison result ERR. Accordingly, an inputwaveform, which is suitable for the phase detection, to the comparator 3is obtained. In the meantime, three threshold values described above arecollectively denoted by Ccomp in FIG. 1.

FIG. 2 is a view illustrating an exemplary selector. The selector 5includes selectors 11-1, 11-2, . . . , 11-n that select comparisonresults Dp1, Dp2, . . . , Dpn or comparison results Dn1, Dn2, . . . ,Dnn that are multiplexed. The comparison results Dp1 to Dpn and Dn1 toDnn are n-bit parallel data and arranged in a row of chronological datain a sequential order of 1 to n.

Further, the selector 5 includes flip-flops (FF) 12-1, 12-2, . . . ,12-n that maintain results selected in the selectors 11-1 to 11-n.Though not illustrated, a clock signal is input to the FFs 12-1 to 12-n,and the FFs 12-1 to 12-n are operated at the same timing to output thedata determination results Do1, Do2, . . . , Don. The operating cycle ofthe FFs 12-1 to 12-n amounts to nUI [time for n bits of the input datasignal Di of the reception circuit 1].

Each of the selectors 11-1 to 11-n outputs each of the comparisonresults Dp1 to Dpn when each of the data determination results Do1 toDon one bit ahead of the current bit is “1”, and outputs each of thecomparison results Dn1 to Dnn when each of the data determinationresults Do1 to Don one bit ahead of the current bit is “0”. Therefore,for example, the selector 11-1 receives the data determination resultDon output from the FF 12-n as an input of a selection signal and theselector 11-2 receives the result selected in the selector 11-1 as aninput of a selection signal. The selector 5 may be implemented with acircuit described above.

Example of Operation of Reception Circuit 1

Hereinafter, an example of operation of the reception circuit 1 of thepresent embodiment will be described. First, the controller 9 detectsthe amplitude of the output data signal of the equalizer 2 from athreshold value at the time when the comparison result ERR of thethreshold value with the output data signal is switched from “0” to “1”or from “1” to “0” by changing the threshold value for error detection.

Hereinafter, it is assumed that the amplitude indicates a differencefrom the center of change to the maximum value or the minimum value ofthe output data signal and the amplitude level indicates magnitude ofthe output data signal at a certain time.

Thereafter, the controller 9 adjusts two threshold values for DFE basedon the detected amplitude. FIG. 3 is a view illustrating examples ofadjustment of two threshold values for DFE. In FIG. 3, the output datasignals having a plurality of data patterns of the equalizer 2 arerepresented to overlap with each other. The horizontal axis indicatestime and the vertical axis indicates amplitude level of the output datasignal. In the meantime, the amplitude of the output data signal isnormalized to “±1”.

Data determination may be accurately performed for an input that has asmall loss, for example, an input which requires a time less than 1UIfor switching data from “0” to “1”, and thus an equalization process maynot be performed on the input. FIG. 3 illustrates an example in which atime for shifting data from “0” to “1” is defined as about 2UI due to aninfluence by ISI (Inter Symbol Interference) caused by adjacent bits.For example, a size of an eye opening in a direction of phase (directionof time) in a case where the determined data one bit ahead of thecurrent bit is 0 (zero) is defined as about 1.5UI. The sampling phase(sampling timing) Tsn may be set to be a phase of the center of the eyeopening in order to increase an accuracy of data determination.

In order to detect a suitable phase, the threshold values Vdp and Vdnmay be set so that positions in the direction of phase of cross pointsbetween data for phase detection, which varies with a specific datapattern, and the threshold values Vdp and Vdn for DFE correspond tophases located at the center of the eye opening. FIG. 3 illustrates theoutput data signal Da1, which has a data pattern of 3-bit continuousdata that is assumed as “011”, of the equalizer 2 and the output datasignal Da2, which has a data pattern of 3-bit continuous data that isassumed as “100”, of the equalizer 2, as an example of the data forphase detection. In the output data signals Da1 and Da2 described above,when a slope is linearly approximated for 1UI where the amplitude levelis changed from “0” to “1” or from “0” to “4”, the threshold value Vdpand the threshold value Vdn may be set to “+0.25” and “−0.25”,respectively. However, since non-linearity is strong near the portion atwhich the amplitude level is “1” or “4”, the period of time needed forshifting data from “0” to “1” or from “1” to “0” becomes slightlysmaller than 2UI and absolute values of the optimal threshold values Vdpand Vdn also become slightly larger than “0.25”. Therefore, in FIG. 3,the threshold value Vdp is set to about “+0.35” and the threshold valueVdn is set to about “−0.35”. The threshold value Vdp and the thresholdvalue Vdn adjusted as described above are set in the comparator 3-2 andthe comparator 3-2, respectively. Adjustment of the threshold value tobe set in the comparator 3-3 will be described later.

Next, descriptions will be made on the data determination process, phasedetection process, and phase adjustment process using the thresholdvalues Vdp and Vdn that are adjusted as described above.

FIG. 4 is a view explaining an example of a data determination process,a phase detection process, and a phase adjustment process. Similarly asin FIG. 3, the output data signals of the equalizer 2 having a pluralityof data patterns are represented to be overlap with each other. Thehorizontal axis indicates time and the vertical axis indicates amplitudelevel of the output data signals. In the meantime, the amplitudes of theoutput data signal are normalized to “±1”.

When a sampling phase is a sampling phase Tsn1 which is ahead of thesampling phase Tsn which becomes the phase of the center of the eyeopening described above, a sample value Ds1 of the output data signalDa1 of the data for phase detection is larger than the threshold valueVdn and smaller than the threshold value Vdp. Therefore, the comparisonresult Dn becomes “1” and the comparison result Dp becomes “0”. Sincethe data determination result Do at a sampling timing ahead of thesampling phase Tsn1 is “0” in the output data signal Da1, the comparisonresult Dn is selected and the data determination result Do is updated inthe selector 5. That is, it is determined that the output data signalDa1 is “1” at the sampling phase Tsn1.

In the meantime, the phase detector 6 detects the phase informationbased on the comparison result Dpn which is not selected in the selector5. In the example of FIG. 4, it is found out that the comparison resultDp is “0” and thus the sampling phase Tsn 1 is ahead of the idealsampling phase Tsn. Therefore, the phase detector 6 outputs “−1” as thephase information UP/DN. Accordingly, the phase shifter 8 adjusts thephase of sampling clock CLKs so as to make the sampling phase slower.

When the sampling phase is a sampling phase Tsn2 which lags behind thesampling phase Tsn which becomes the phase of the center of the eyeopening described above, a sample value Ds2 of the output data signalDa1 of the data for phase detection is larger than the threshold valueVdn and the threshold value Vdp. Therefore, the comparison result Dnbecomes “1” and the comparison result Dp also becomes “1”. Since thedata determination result Do at a sampling timing ahead of the samplingphase Tsn1 is “0” in the output data signal Da1, the comparison resultDn is selected and the data determination result Do is updated in theselector 5. That is, it is also determined that the output data signalDa1 is “1” at the sampling phase Tsn2.

In the meantime, the phase detector 6 detects the phase informationbased on the comparison result Dp which is not selected in the selector5. In the example of FIG. 4, it is found out that the comparison resultDp is “1” and thus the sampling phase Tsn2 lags behind the idealsampling phase Tsn. Therefore, the phase detector 6 outputs “+1” as thephase information UP/DN. Accordingly, the phase shifter 8 adjusts thephase of sampling clock CLKs so as to make the sampling phase faster.

The same data determination process, phase detection process, and phaseadjustment process may be applied even when the output data signal Da2having a data pattern which is “100” is set as the data for phasedetection. When a sampling phase is the sampling phase Tsn1 which isahead of the sampling phase Tsn which becomes the phase of the center ofthe eye opening described above, a sample value Ds3 of the output datasignal Da2 of the data for phase detection is larger than the thresholdvalue Vdn and smaller than the threshold value Vdp. Therefore, thecomparison result Dn becomes “1” and the comparison result Dp becomes“0”. Since the data determination result Do at a sampling timing aheadof the sampling phase Tsn1 is “1” in the output data signal Da2, thecomparison result Dp is selected and the data determination result Do isupdated in the selector 5. That is, it is determined that the outputdata signal Da1 is “0” at the sampling phase Tsn1.

In the meantime, the phase detector 6 detects the phase informationbased on the comparison result Dnn which is not selected in the selector5. In the example of FIG. 4, it is found out that the comparison resultDn is “1” and thus the sampling phase Tsn1 is ahead of the idealsampling phase Tsn. Therefore, the phase detector 6 outputs “−1” as thephase information UP/DN. Accordingly, the phase shifter 8 adjusts thephase of sampling clock CLKs so as to make the sampling phase slower.

When a sampling phase is a sampling phase Tsn2 which lags behind thesampling phase Tsn which becomes the phase of the center of the eyeopening described above, a sample value Ds4 of the output data signalDa2 of the data for phase detection is smaller than the threshold valueVdn and the threshold value Vdp. Therefore, the comparison result Dnbecomes “0” and the comparison result Dp also becomes “0”. Since thedata determination result Do at the sampling timing ahead of thesampling phase Tsn1 is “1” in the output data signal Da2, the comparisonresult Dp is selected and the data determination result Do is updated inthe selector 5. That is, it is also determined that the output datasignal Da1 is “1” at the sampling phase Tsn2.

In the meantime, the phase detector 6 detects the phase informationbased on the comparison result Dnn which is not selected in the selector5. In the example of FIG. 4, it is found out that the comparison resultDn is “0” and thus the sampling phase Tsn2 lags behind the idealsampling phase Tsn. Therefore, the phase detector 6 outputs “+1” as thephase information UP/DN. Accordingly, the phase shifter 8 adjusts thephase of sampling clock CLKs so as to make the sampling phase faster.

FIG. 5 is a view illustrating an example of a phase detection algorithm.FIG. 5 is a summary of phase detection algorithm as illustrated in FIG.4. Dn−1 and Dn+1 indicate an (n−1)-th bit data determination result andan (n+1)-th bit data determination result, respectively. Dp_n and Dn_nindicate an n-th bit comparison result Dp and an n-th bit comparisonresult Dn, respectively.

When a data pattern is “011”, that is, Dn−1 is “0” and Dn_n and Dn+1 are“1”, the phase information UP/DN is changed according to a value ofDp_n. For example, when Dp_n is “1”, the phase information UP/DN becomes“+1” and when Dp_n is “0”, the phase information UP/DN becomes “−1”.

When a data pattern is “100”, that is, Dn−1 is “1” and Dp_n and Dn+1 are“0”, the phase information UP/DN is changed according to a value ofDn_n. For example, when Dn_n is “0”, the phase information UP/DN becomes“+1”, and when Dn_n is “1”, the phase information UP/DN becomes “−1”.

In the meantime, in the example of FIG. 5, when another data pattern isinput, the phase information UP/DN becomes “0”. Although the phasedetection algorithm described above represents an example in which thephase information UP/DN is detected based on a specific data pattern ofthree bits, the phase detection algorithm is not limited thereto. Thephase detection algorithm may be configured to detect the phaseinformation UP/DN based on a specific data pattern of two or four bitsin the three bits may be in the phase detection algorithm.

The phase information UP/DN obtained as described above is input to thefilter 7 and the filter 7 filters the phase information UP/DN togenerate the phase adjustment code Pcode. Accordingly, a phaseadjustment of the sampling clock CLKs is performed by the phase shifter8. As illustrated in FIG. 4, in a case of the sampling phase Tsn1, thephase shifter 8 performs an adjustment which delays a phase so that thesampling phase Tsn1 comes near the ideal sampling phase Tsn. In a caseof the sampling phase Tsn2, the phase shifter 8 performs an adjustmentwhich advances a phase to cause the sampling phase Tsn2 to be near theideal sampling phase Tsn.

The controller 9 waits for a predetermined time in order to wait for thesampling phase to be converged with respect to the threshold values Vdpand Vdn. Thereafter, the controller 9 sets the threshold value for errordetection based on the threshold values Vdp and Vdnn and adaptivelycontrols an equalization coefficient Ceq of the equalizer 2.

FIG. 6 is a view illustrating an example of a threshold value for errordetection. FIG. 6 illustrates threshold values Vpp1, Vpp2, Vpn1 and Vpn2for error detection, in addition to the threshold values Vdp and Vdnillustrated in FIG. 3 and FIG. 4.

Here, the threshold value Vpp1 is a value obtained by adding anexpectation value of the amplitude of the output data signal after theequalization process to the threshold value Vdp, and the threshold valueVpp2 is a value obtained by subtracting the expectation value of theamplitude of the output data signal after the equalization process fromthe threshold value Vdp. Further, the threshold value Vpn1 is a valueobtained by adding an expectation value of the amplitude of the outputdata signal after the equalization process to the threshold value Vdn,and the threshold value Vpn2 is a value obtained by subtracting theexpectation value of the amplitude of the output data signal after theequalization process from the threshold value Vdn.

An adjustment velocity of the equalization coefficient Ceq may be slowerthan a phase adjustment velocity and thus, the controller 9 sequentiallyshifts the threshold value Vpp1, Vpp2, Vpn1 and Vpn2 to be set in thecomparator 3-3. Also, when the output data signal of the equalizer 2 islarger than a threshold value which is set in the comparator 3-3, thecomparison result ERR becomes “1”. When the output data signal of theequalizer 2 is smaller than the threshold value, the comparison resultERR becomes “0”.

Assuming that the LMS (Least Mean Square) algorithm is used, thecontroller 9 adjusts the equalization coefficient Ceq based on thefollowing Equation (1), based on the comparison result ERR.Ceqn+1=Ceqn+μERRnDn−1  (1)

In Equation (1), “Ceqn+1” is an equalization coefficient Ceq at (n+1)-thcycle and “Ceqn” is an equalization coefficient Ceq at n-th cycle. “p”is a quantity (step width) which increases the equalization coefficientCeq at the next cycle upon the error detection. The “ERRn” correspondsto a comparison result ERR at n-th cycle and the “Dn−1” is a datadetermination result at (n−1)-th cycle. In the meantime, the “ERRn” maybe represented by the following Equation (2).ERRn=Yn−dDn  (2)

In Equation (2), “Yn” is the amplitude of the output data signal beforethe data determination after the equalization process at n-th cycle, “d”is an expectation value of the amplitude of the output after theequalization process described above, and “Dn” is the data determinationresult at n-th cycle. However, the “ERRn” becomes “0” or “1” indicatedby the comparison results of the amplitude of the output data signalwith the threshold values Vpp1, Vpp2, Vpn1 and Vpn2 and an arithmeticoperation of Equation (2) is not performed in the present embodiment, asdescribed above.

FIG. 7 is a view illustrating an example of an output data signal of anequalizer when an equalization level is low. The output data signalsDa5, Da6, Da1 and Da8 illustrated in FIG. 7 are the sampling phasesright before the sampling phase Tsn and are determined as having thedata determination result of “1”. The error detection is performed forthe output data signals Da5, Da6, Da7 and Da8 using the thresholdvaluesVpp1 and Vpp2 obtained by adding or subtracting the expectationvalue “d” to and from the threshold value Vdp.

When the equalization level is low, the output data signals Da5, Da6,Da7 and Da8 exceed the threshold values Vpp1 and Vpp2 and thus aprobability that the comparison result ERR becomes 1 is high. In theexample of FIG. 7, when the threshold value for error detection is setas the threshold value Vpp1, the output data signal Da5 is larger thanthe threshold value Vpp1 and thus the comparison result ERR becomes 1.The output data signals Da6, Da7 and Da8 other than the output datasignal Da5 are smaller than the threshold value Vpp1 and thus thecomparison result ERR becomes 0. In the meantime, when the thresholdvalue for error detection is set as the threshold value Vpp2, the outputdata signals Da5, Da6, Da7 and Da8 are larger than the threshold valueVpp2 and thus all the comparison results ERR become 1. Accordingly, theprobability that the comparison result ERR becomes 1 increases as atotal.

When the probability that the comparison result ERR becomes 1 is high,the equalization coefficient Ceq is increased by the controller 9. Inthe meantime, an error detection using the threshold values Vpn1 andVpn2 illustrated in FIG. 6 is performed in the same manner. Performingthe error detection by sequentially shifting the threshold values Vpp1,Vpp2, Vpn1 and Vpn2 and adjusting the equalization coefficient Ceq areto maintain symmetry of input waveforms to the comparator 3. Further,since the threshold values Vpp1, Vpp2, Vpn1 and Vpn2 are set in the samecomparator 3-3 at different timings, an increase of the number ofcomparators is not caused and thus an increase of a circuit area may besuppressed.

The controller 9 repeats a processing of waiting for the sampling phaseto be converged with respect to the threshold values Vdp and Vdn and aprocessing of adjusting the equalization coefficient Ceq, and determinesthat the sampling phase is converged at the time when an amount ofchange of the equalization coefficient Ceq falls within a predeterminedrange. Accordingly, the reception circuit 1 completes an initialoperation and proceeds to a normal operation.

FIG. 8 is a view illustrating an example of an output data signal of anequalizer after optimization of an equalization level. In the example ofFIG. 8, when the threshold value for error detection is set as thethreshold value Vpp1, the output data signal Da5 is larger than thethreshold value Vpp1 and thus the comparison result ERR becomes 1. Theoutput data signals Da6, Da7 and Da8 other than the output data signalDa5 are smaller than the threshold value Vpp1 and thus the comparisonresult ERR becomes 0. In the meantime, when the threshold value forerror detection is set as the threshold value Vpp2, the output datasignal Da8 is larger than the threshold value Vpp1 and thus all thecomparison results ERR become 0. The output data signals Da5, Da6 andDa7 other than the output data signal Da8 are larger than the thresholdvalue Vpp1 and thus the comparison result ERR becomes 1. Accordingly,the probability that the comparison result ERR becomes 1 becomes thesame as the probability that the comparison result ERR becomes 0, sothat the sampling phase is converged.

FIG. 9 is a view illustrating the example of an output signal of aselector after a phase adjustment and an equalization level optimizationin an analog waveform. The output signal (data determination result Do)of the selector 5 is a signal consisting of zeros and ones (0/1) andthus, the waveform of the output signal may not be actually drawn.However, a result of a speculative DFE processing by the receptioncircuit 1 is represented in an analog waveform, for explanation.

The threshold values Vdp and Vdn shift to 0 (zero) by the speculativeDFE processing using the threshold value Vpp1, Vpp2, Vpn1, and Vpn2, andalso the waveforms also shift simultaneously to become waveforms havingan amplitude of the expectation value “d” illustrated in FIG. 9.Further, a waveform in which the sampling phase Tsn becomes the centerof the eye opening is obtained.

As described above, the reception circuit 1 of the present embodimentuses one of the threshold values Vdp and Vdn for DFE for the datadetermination and uses the other of the threshold values Vdp and Vdn forthe phase detection, based on the data determination result at asampling phase right before the current sampling phase. Accordingly, thethreshold value for the phase detection may not be added and thus anincrease of the number of comparators may be suppressed. Accordingly, itis possible to implement the reception circuit 1 which performs thespeculative DFE and the baud rate tracking CDR in a small-scale circuit.

Further, when the number of comparators is small, the data buffer orclock buffer which drives the comparator may be implemented in a smallscale. Therefore, the circuit size may be reduced and low powerconsumption may be achieved. Further, an equalization coefficient isadaptively adjusted in such a manner that the threshold values Vdp andVdn for DFE are set according to the amplitude of the output data signalof the equalizer 2 and the threshold value for error detection are setbased on the threshold values Vdp and Vdn. Therefore, a waveform inwhich the set sampling phase is located at an appropriate position maybe generated.

In the meantime, the description has been made on the reception circuit1 having the functionality of a 1-tap speculative DFE, but may also beadapted for a multi-tap DFE. In such a case, when a speculative DFE isarranged at a first tap for which a strict velocity of the feedback loopis required and DFEs are arranged at a second tap and on, the receptioncircuit 1 illustrated in FIG. 1 may be applied as it is. When a two ormore-tap speculative DFE is applied, the number of threshold values tobe set increases. Hereinafter, a reception circuit having functionalityof a two-tap speculative DFE will be described as an example.

Second Embodiment

FIG. 10 is a view illustrating an exemplary reception circuit accordingto a second embodiment. Similar constitutional elements as thoseillustrated in FIG. 1 are denoted by similar reference numerals anddescriptions thereof will be omitted.

A comparator 3 a of a reception circuit 1 a includes comparators 3-1 a,3-1 b, 3-2 a, 3-2 b and 3-3 in order to implement a two-tap speculativeDFE. The threshold value for DFE is set by the controller 9 a in thecomparator 3-1 a, 3-b, 3-2 a, 3-2 b.

FIG. 11 is a view illustrating an example of a threshold value settingfor DFE in the reception circuit according to the second embodiment. InFIG. 11, the output data signals of the equalizer 2 having a pluralityof data patterns are represented to overlap with each other. Thehorizontal axis indicates time and the vertical axis indicates amplitudelevel of the output data signal. In the meantime, the amplitude of theoutput data signal is normalized to “±1”.

When the data determination results Do one bit ahead and two bits aheadwith respect to a bit determined at the timing of the sampling phase Tsnare 1 (one), the comparison result Dpp for which the threshold valueVdpp is used is selected as the data determination result Do in thesampling phase Tsn in a selector 5 a. Further, a phase detector 6 adetects phase information according to the comparison result Dnpobtained using the threshold value Vdnp, which is not used for the datadetermination.

When the data determination result Do of a bit 1 bit ahead is 1 and thedata determination result Do of a bit 2 bits ahead with respect to a bitdetermined at the timing of the sampling phase Tsn is 0, the comparisonresult Dpn obtained using the threshold value Vdpn is selected as thedata determination result Do. Further, the phase detector 6 a detectsphase information according to the comparison result Dnn obtained usingthe threshold value Vdnn, which is not used for the data determination.

When the data determination result Do of a bit 1 bit ahead with respectto a bit determined at the timing of the sampling phase Tsn is 0 and thedata determination result Do of a bit 2 bits ahead with respect to a bitdetermined at the timing of the sampling phase Tsn is 1, the comparisonresult Dnp obtained using the threshold value Vdpn is selected as thedata determination result Do. Further, the phase detector 6 a detects aphase information according to the comparison result Dpp obtained usingthe threshold value Vdpp, which is not used for the data determination.

When the data determination results Do one bit ahead and two bits aheadwith respect to a bit determined at the timing of the sampling phase Tsnare 0, the comparison result Dnn obtained using the threshold value Vdnnis selected as the data determination result Do. Further, the phasedetector 6 a detects a phase information according to the comparisonresult Dpn obtained using the threshold value Vdpn, which is not usedfor the data determination.

In the meantime, the threshold values Vdpp, Vdpn, Vdnp and Vdnn areadjusted based on the amplitude of the output data signal of theequalizer 2 detected in the controller 9 a, similarly to the thresholdvalues Vdp and Vdn in the reception circuit 1 of the first embodiment.

The threshold values Vdpp, Vdpn, Vdnp and Vdnn may be set so thatpositions in the direction of phase of cross points between data forphase detection and the threshold values Vdpp, Vdpn, Vdnp and Vdnncorrespond to phases located at the center of the eye opening in orderto detect the phase deviation to the ideal sampling phase Tsn. In theexample of FIG. 11, the threshold value Vdpp is set to “+0.4”, thethreshold value Vdpn is set to “+0.3”, the threshold value Vdnp is setto “−0.3”, and the threshold value Vdnn is set to “−0.4” for a casewhere the amplitude of the output data signal of the equalizer 2 isnormalized to “±1”.

FIG. 12 is a view illustrating another example of the phase detectionalgorithm. Dn−2 indicates an (n−2)-th bit data determination result,Dn−1 indicates an (n−1)-th bit data determination result, and Dn+1indicates (n+1)-th bit data determination result. Dpp_n, Dpn_n, Dnp_n,and Dnn_n indicate n-th bit comparison results Dpp, Dpn, Dnp, and Dnn,respectively.

When a data pattern of bits from (n−2)-th bit to (n+1)-th bit is “0011”,the phase information UP/DN is changed according to a value of Dpn_n.For example, when Dpn_n is 1, the phase information UP/DN becomes+1, andwhen Dpn_n is 0, the phase information UP/DN becomes “−1”.

When a data pattern of bits from (n−2)-th bit to (n+1)-th bit is “1011”,the phase information UP/DN is changed according to a value of Dpp_n.For example, when Dpp_n is 1, the phase information UP/DN becomes +1,and when Dpp_n is 0, the phase information UP/DN becomes “−1”.

When a data pattern of bits from (n−2)-th bit to (n+1)-th bit is “0100”,the phase information UP/DN is changed according to a value of Dnn_n.For example, when Dnn_n is 0, the phase information UP/DN becomes +1,and when Dnn_n is 1, the phase information UP/DN becomes “−1”.

When a data pattern of bits from (n−2)-th bit to (n+1)-th bit is “1100”,the phase information UP/DN is changed according to a value of Dnp_n.For example, when Dnp_n is 0, the phase information UP/DN becomes “+1”,and when Dnp_n is 1, the phase information UP/DN becomes “−1”.

In the meantime, in the example of FIG. 12, when other data patterns areinput, the phase information UP/DN becomes 0. As described above, thephase shifter 8 performs the phase adjustment using the phase adjustmentcode Pcode generated in the filter 7 based on the phase informationUP/DNn obtained in the phase detector 6 a.

The equalization coefficient Ceq is adjusted similarly as in thereception circuit 1 of the first embodiment but the threshold value forerror detection is obtained by adding or subtracting the expectationvalue “d” described above to or from each of the threshold values Vdpp,Vdpn, Vdnp, and Vdnn for DFE.

In the meantime, an example of the selector 5 a in the reception circuit1 a of the second embodiment is implemented by, for example, a circuitas follows.

FIG. 13 is a view illustrating an exemplary selector in the receptioncircuit according to the second embodiment. The selector 5 a includesselectors 13-1 a, 13-2 a, . . . , 13-na that select one of thecomparison results Dpp1, Dpp2, . . . , Dppn and the comparison resultsDpn1, Dpn2, . . . , Dpnn that are multiplexed. Further, the selector 5 aincludes selectors 13-1 b, 13-2 b, . . . 13-nb that select one of thecomparison results Dnp1, Dnp2, Dnpn and the comparison results Dnn1,Dnn2, . . . , Dnnn that are multiplexed. In the meantime, the comparisonresults Dpp1 to Dppn, Dpn1 to Dpnn, Dnp1 to Dnpn, and Dnn1 to Dnnn aren-bit parallel data and arranged in a row of chronological data in asequential order of 1 to n.

Further, the selector 5 a includes selectors 14-1, 14-2, . . . , 14-nthat select one of output signals of the selectors 13-1 a to 13-na orthe selectors 13-1 b to 13-nb. Further, the selector 5 a includes FFs15-1, 15-2, . . . , 15-n that maintain the results selected in theselectors 14-1 to 14-n. Though not illustrated, a clock signal is inputto the FFs 15-1 to 15-n and the FFs 15-1 to 15-n are operated at thesame timing to output the data determination results Do1, Dot, . . . ,Don. The operating cycle of the FFs 15-1 to 15-n amounts to nUI [timefor n bits of the input data signal Di of the reception circuit 1].

When the data determination result Don two bits ahead is 1, theselectors 13-1 a to 13-na and 13-1 b to 13-nb at the first stage selectthe comparison results Dpp1 to Dppn and the comparison results Dnp1 toDnpn. When the data determination result Don two bits ahead is 0, theselectors 13-1 a to 13-na and 13-1 b to 13-nb select the comparisonresults Dpn1 to Dpnn and the comparison results Dnn1-Dnnn.

The selectors 14-1-14-n at the second stage select the output signals ofthe selectors 13-1 a to 13-na when the data determination result Do1 toDon one bit ahead is 1, and select the output signals of the selectors13-1 b to 13-nb when the data determination result Do1 to Don one bitahead is 0.

The selector 5 a may be implemented by the circuits described above. Thecomparator which compares the threshold value for phase detection withthe output data signal of the equalizer 2 also does not need to beinstalled in the reception circuit 1 a of the second embodiment whichcorresponds to the two-tap speculative DFE described above, and thus itis possible to suppress an increase of a circuit area may be suppressed.

Third Embodiment

FIG. 14 is a view illustrating an exemplary reception circuit accordingto a third embodiment. Similar constitutional elements as thoseillustrated in FIG. 1 are denoted by similar reference numerals anddescriptions thereof will be omitted.

A reception circuit 1 b of the third embodiment is configured by acircuit with which an interleaving operation may be performed.Accordingly, even when the frequency of the input data signal Di isfast, the reception circuit 1 b may be operated by performing a parallelprocessing.

A comparator 3 b of the reception circuit 1 b is configured in aparallel architecture of the comparators 3 a-1, 3 a-2, 3 a-3 and thecomparators 3 b-1, 3 b-2, 3 b-3 in order to allow the interleavingoperation to be performed.

The same threshold value [negative side (see FIG. 3)] for DFE is set bythe controller 9 in the comparators 3 a-1 and 3 b-1. The same thresholdvalue [positive side (see FIG. 3)] for DFE is set by the controller 9 inthe comparators 3 a-2 and 3 b-2. Further, the same threshold value forerror detection is set by the controller 9 in the comparators 3 a-3 and3 b-3.

The comparators 3 a-1, 3 a-2 and 3 a-3 are driven by a sampling clockCLKs1 and the comparators 3 b-1, 3 b-2 and 3 b-3 are driven by asampling clock CLKs2. The phase difference between the sampling clockCLKs1 and the sampling clock CLKs2 corresponds to, for example, the sizeof 1 UI of the input data signal Di.

The respective comparators 3 a-1, 3 a-2 and 3 a-3 output the comparisonresults Dn1, Dp1 and ERR1, respectively. In the meantime, the respectivecomparators 3 b-1, 3 b-2 and 3 b-3 output the comparison results Dn2,Dp2 and ERR2, respectively. Further, a DMX 4 b inverse-multiplexes 2(two) bits into n bits to be output in the reception circuit 1 b of thepresent embodiment. The DMX 4 b inverse-multiplexes 2 (two) bits of Dn1and Dn22, each of which is 1 (one) bit, into n bits to be output as thecomparison result Dn, and 2 (two) bits of Dp1 and Dp22, each of which is1 (one) bit, into n bits to be output as the comparison result Dp.Further, the DMX 4 b inverse-multiplexes 2 (two) bits of ERR1 and ERR2,each of which is 1 (one) bit, into n bits to be output as the comparisonresult ERR.

Operations other than the interleaving operation are the same as in thereception circuit 1 of the first embodiment and the same effect as inthe reception circuit 1 of the first embodiment may be achieved. In themeantime, the reception circuit 1 b is a circuit which performs theinterleaving operation with two-parallelism, but the number of paralleloperations is not limited thereto and three or more-parallelism may beadopted.

Fourth Embodiment

FIG. 15 is a view illustrating an exemplary reception circuit accordingto a fourth embodiment. Similar constitutional elements as those of thereception circuit 1 illustrated in FIG. 1 are denoted by similarreference numerals, and descriptions thereof will be omitted.

The output data signal of the equalizer 2 is directly input to thecomparator 3 to adjust the threshold value to be set in the comparator 3in the reception circuit 1 of the first embodiment. In contrast, areception circuit 1 c of the fourth embodiment fixes the threshold valueto be set in the comparator 3 and adjusts the respective amplitudes ofthe output data signals of the equalizer 2 to be input to thecomparators 3-1, 3-2 and 3-3 to levels according to the respectivethreshold values, respectively. The threshold value itself is fixed to,for example, a half of the amplitude of the output data signal in thereception circuit 1 c of the fourth embodiment.

Therefore, the controller 9 b of the reception circuit 1 c includes anaddition-subtraction unit 20 and an equalization coefficient generator21. The equalization coefficient generator 21 has the same functionalityas that of the controller 9 illustrated in FIG. 1 but supplies a valueto the addition-subtraction unit 20 instead of setting the thresholdvalue in the comparator 3.

The addition-subtraction unit 20 includes an adder 20 a which adds anequalization coefficient Cdfe to the output data signal of the equalizer2 and a subtractor 20 b which subtracts the equalization coefficientCdfe from the output data signal of the equalizer 2. Further, theaddition-subtraction unit 20 includes an adder-subtractor 20 c whichadds or subtracts an equalization coefficient Cerr, which is accordingto an error level intended to be detected, to or from the output datasignal of the equalizer 2.

The equalization coefficients Cdfe and Cerr are supplied to theaddition-subtraction unit 20 by the equalization coefficient generator21. The equalization coefficient Cdfe is determined based on theamplitude of the output data signal and has the same size of, forexample, the threshold values Vdn and Vdp described above. Theequalization coefficient Cerr is obtained by adding or subtracting theequalization coefficient Cdfe to or from the expectation value “d”,similarly to the relationship between the threshold values Vdn and Vdpand the threshold value for error detection.

The output of the adder 20 a is input to the comparator 3-1 and thecomparison result Dn resulted from the comparison of the input valuewith the fixed threshold value is output from the comparator 3-1. Theoutput of the subtractor 20 b is input to the comparator 3-2 and thecomparison result Dp resulted from the comparison of the input valuewith the fixed threshold value is output from the comparator 3-2.

The output of the adder-subtractor 20 c is input to the comparator 3-3and the comparison result ERR resulted from the comparison of the inputvalue with the fixed threshold value is output from the comparator 3-3.The comparison results Dp, Dn and ERR output from the comparators 3-1,3-2 and 3-3 becomes the same value those obtained by the receptioncircuit 1, respectively. Therefore, other operations are the same asthose of the reception circuit 1 of the first embodiment and the sameeffect as that of the reception circuit 1 of the first embodiment may beobtained in the reception circuit 1 c illustrated in FIG. 15.

As described above, an aspect of the present disclosure has beendescribed based on the embodiments, but these embodiments areillustrative only and are not meant to be limited to the mattersdescribed above. For example, the embodiments may be appropriatelycombined.

All examples and conditional language recited herein are intended forpedagogical purposes to aid the reader in understanding the inventionand the concepts contributed by the inventor to furthering the art, andare to be construed as being without limitation to such specificallyrecited examples and conditions, nor does the organization of suchexamples in the specification relate to a showing of the superiority andinferiority of the invention. Although the embodiments of the presentinvention have been described in detail, it should be understood thatthe various changes, substitutions, and alterations could be made heretowithout departing from the spirit and scope of the invention.

What is claimed is:
 1. A reception circuit to reproduce a data signalbased on a data determination result of determining an amplitude levelof an input data signal at a sampling timing synchronized with asampling clock, the reception circuit comprising: an equalizerconfigured to perform an equalization process on the input data signal;a comparator configured to compare an output data signal of theequalizer with a first threshold value, a second threshold value, and athird threshold value at a first sampling timing to output a firstcomparison result, a second comparison result, and a third comparisonresult, respectively; a selector configured to select any one of thefirst comparison result and the second comparison result based on thedata determination result at a second sampling timing before the firstsampling timing, and update the data determination result; a phasedetector configured to detect phase information based on the firstcomparison result or the second comparison result which is not selectedby the selector; a phase shifter configured to adjust a phase of thesampling clock based on the phase information detected by the phasedetector; and a controller configured to set the third threshold valuebased on the first threshold value and the second threshold value byeither adjusting the first threshold value and the second thresholdvalue based on the amplitude of the output data signal or adding orsubtracting a first value to or from the output data signal, detect anequalization result at the equalizer based on the third comparisonresult by the set third threshold value, and adjust an equalizationcoefficient of the equalizer based on the detected equalization result.2. The reception circuit according to claim 1, wherein the phasedetector is configured to detect whether a phase of the sampling clocklags behind a phase of the output data signal based on whether amplitudeof the output data signal, which varies with a first data pattern, atthe first sampling timing is larger than the first threshold value orthe second threshold value.
 3. The reception circuit according to claim1, wherein the controller is configured to add or subtract anexpectation value of the amplitude of the output data signal to or fromthe first threshold value or the second threshold value so as to set aplurality of third threshold values at different timings, and adjust theequalization coefficient so that an occurrence probability of a statewhere the third comparison result indicates that an amplitude level ofthe output data signal having the plurality of data patterns exceeds thethird threshold value becomes equal to an occurrence probability of astate where the third comparison result indicates that an amplitudelevel of the output data signal having the plurality of data patternsdoes not exceed the third threshold value.
 4. The reception circuitaccording to claim 2, wherein the controller is configured to adjust thefirst threshold value or the second threshold value so that a phase of across point between the first threshold value or the second thresholdvalue and the output data signal, which varies with the first datapattern is located at the center of an eye opening formed by the outputdata signal having the plurality of data patterns.
 5. The receptioncircuit according to claim 1, wherein the first threshold value or thesecond threshold value is a half of the amplitude of the output datasignal, the, controller is configured to control the first value basedon the amplitude of the output data signal, and the comparator isconfigured to compare the output data signal to or from which the firstvalue is added or subtracted, with the first threshold value and thesecond threshold value to output the first comparison result and thesecond comparison result, respectively.